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| om PRELIMINARY CYP32G0401DX .c 4U Multi-Mode Quad HOTLink-IIITM Transceiver Multi-Gigabit et Features Functional Description he aS at .D w w w Third-generation HOTLink(R) technology 2488- to 3125-Mbps signaling rate per serial link XAUI/10G Ethernet compatible mode InfiniBandTM compatible Programmable 8-bit or 10-bit SERDES Selectable 8B/10B encoding/decoding Ethernet PCS functions using the IEEE802.3z ordered set state machine * Programmable receive framer provides alignment to -- A1/A2: SONET/SDH * * * * * * * * * * * -- 8B/10B COMMA: Ethernet, InfiniBand, XAUI Synchronous SSTL_2 parallel input/output interface Internal PLLs with no external PLL components Differential CML serial inputs per channel Differential CML serial outputs per channel -- Source matched for 50 transmission lines The CYP32G0401DX Quad HOTLink-IIITM Transceiver is a point-to-point communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 2488 to 3125 Mbps per serial link. -- No external bias resistors required * Compatible with -- Fiber-optic modules -- Copper cables -- Circuit board traces * Diagnostic loop back and line loop back * Signal detect input * Low Power (2.5W typical) -- Single +2.5V VDD supply * 256-ball Thermally Enhanced BGA * Commercial temperature range 0C to +70C * Industrial temperature range -40C to +85C m o .c U t4 e e h S ta a .D w w w 10 Serial Links 10 10 10 10 10 Serial Links 10 CYP32G0401DX CYP32G0401DX 10 10 10 10 Serial Links 10 10 10 10 Serial Links Backplane or Cabled Connections 10 Each transmit channel accepts parallel characters in an Input Register, encodes each character for transport, and converts it to serial data. Each receive channel accepts serial data and converts it to parallel data, decodes the data into characters, and presents these characters to an output register. Figure 1 illustrates typical connections between independent host systems and corresponding CYP32G0401DX parts. As a thirdgeneration HOTLink transceiver, the CYP32G0401DX extends the HOTLink family with enhanced levels of integration, multi-gigabit data rates, and multi-mode versatility. The transmit section of the CYP32G0401DX Quad HOTLinkIII shown in Figure 2 consists of four channels. Each channel can accept either 8-bit data characters or pre-encoded 10-bit transmission characters. Data characters are passed from the Transmit Input Register to an embedded bypassable 8B/10B Encoder to improve their serial transmission characteristics. These encoded characters are then serialized and output from Current Mode Logic (CML) differential transmission-line drivers at a bit-rate which is a multiple of the input reference clock. The receive section of the CYP32G0401DX Quad HOTLink-III consists of four channels. Each channel accepts a serial bitstream from a CML differential line receiver and, using a completely integrated PLL Clock Synchronizer, recovers the timing information necessary for data reconstruction. Each recovered bit-stream is deserialized and framed into characters, 8B/10B decoded, and checked for transmission errors. Recovered decoded characters are then written to an internal Elasticity Buffer, and presented to the destination host system. The integrated 8B/10B encoder/decoder may be bypassed for systems that present externally encoded or scrambled data at the parallel interface. Figure 1. HOTLink-IIITM System Connections Cypress Semiconductor Corporation Document #: 38-02019 Rev. *C * 3901 North First Street * San Jose om .c 4U et he aS at .D w w w * CA 95134 * 408-943-2600 Revised November 7, 2001 System Host System Host PRELIMINARY The parallel I/O interface may be configured for numerous forms of clocking to provide the highest flexibility in system architecture. The receive interface may be configured to present data relative to a recovered clock (output) or to a local reference clock (input). The CYP32G0401DX is illustrated in greater detail in Figure 3. RXDb[7:0] RXDVb,RXERb CRSb, COLb TXDb[7:0] TXENb,TXERb CYP32G0401DX HOTLink-III devices are ideal for a variety of applications where parallel interfaces can be replaced with high-speed, point-to-point serial links. Some applications include interconnecting workstations, backplanes, servers, mass storage, and video transmission equipment. RXDa[7:0] RXDVa,RXERa CRSa, COLa TXDa[7:0] TXENa,TXERa x10 x12 x10 x12 x10 x12 x10 Phase Align FIFO Encoder 8B/10B Elasticity FIFO Decoder 8B/10B Framer Phase Align FIFO Encoder 8B/10B Elasticity FIFO Decoder 8B/10B Framer Phase Align FIFO Encoder 8B/10B Elasticity FIFO Decoder 8B/10B Framer Phase Align FIFO Encoder 8B/10B Elasticity FIFO Decoder 8B/10B Framer Serializer Deserializer Serializer Deserializer Serializer Deserializer Serializer Deserializer TX RX TX RX TX RX TX RXPa RXNa TXPa TXNa RXPb RXNb TXPb TXNb Figure 2. CYP32G0401DX Transceiver Logic Block Diagram Document #: 38-02019 Rev. *C RXPc RXNc RXPd RXNd Page 2 of 34 TXPc TXNc TXPd TXNd RXDd[7:0] RXDVd,RXERd CRSd, COLd x12 RXDc[7:0] RXDVc,RXERc CRSc, COLc TXDd[7:0] TXENd,TXERd TXDc[7:0] TXENc,TXERc RX PRELIMINARY CYP32G0401DX Channel a TXD[7:0] TXEN TXER GTXCLK 8 PHASE ALIGN FIFO CI CO 8B/10B ENCODER PCS LAYER PAR TO SER RE-TIME LINE DRIVER TXP TXN CKI CKQ 8B/10B Bypass CLOCK RECOVERY DPLL RXD[7:0] RXER RXDV CRS COL RCLKIN OOF 8 ELASTICITY FIFO 8B/10B DECODER PCS LAYER CLK FRAME FRP ALIGNMENT CLK SER TO PAR RXP DATA RECOVERY LINE RCVR RXN CO CI LOSS OF SIGNAL LOS POL RXCLK TIMING DIVIDE BY 8 or 10 TCLKOUT FRAME ENCODE SER8_10 FRSYN[1:0] LBEN TEST MDIO MDC RESETN MANAGEMENT INTERFACE/ 2 Channel b TIMING DIVIDE BY 8 or 10 Channel c Channel d TEST/ AUTO-NEG 2 REFP REFN FREQUENCY SYNTHESIZER PHASE-LOCKED LOOP 2 ANTEST[1:0] Figure 3. CYP32G0401DX Transceiver Block Diagram Document #: 38-02019 Rev. *C Page 3 of 34 PRELIMINARY Pin Configuration (Top View) 1 A DGND CYP32G0401DX 2 DGND 3 DGND 4 RCLKINc 5 RXD2c 6 RXCLKc 7 GTXCLKc 8 TXD5c 9 DGND 10 DGND 11 TCLKOUT 12 GTXCLKb 13 DGND 14 TXD4b 15 RCLKINb 16 RXD7b 17 RXCLKb 18 DGND 19 DGND 20 DGND B DGND DVDD DVDD RXD5c RXD3c RXD0c TXD1c TXD3c TXD7c TXENc VDIGCc TXD0b TXD2b TXD5b RXDVb RXD6b RXD4b DVDD DVDD DGND C DGND DVDD DVDD RXD7c RXD4c RXD1c COLc TXD2c TXD6c TXERc TSYNC TXD1b TXD3b TXD7b TXENb RXD5b RXD3b DVDD DVDD DGND D OOFd RXDVc RXERc DVDD RXD6c CRSc DVDD TXD0c TXD4c DVDD GDIGCc GDIGCb TXD6b DVDD TXERb RXERb DVDD RXD2b RXD1b RXD0b E RXCLKd RXD7d RXDVd OOFc COLb CRSb OOFa RXCLKa F RXD4d RXD5d RXD6d RXERd OOFb RXDVa RXERa RXD7a G RCLKINd RXD2d RXD3d GDIGCd GDIGCa RXD6a RXD4a RXD3a H DGND RXD0d RXD1d COLd RXD5a RXD2a CRSa RCLKINa J GTXCLKd TXD1d TXD0d CRSd RXD1a RXD0a COLa DGND K TXD5d TXD4d TXD3d TXD2d DVDD TXD0a GTXCLKa DGND L DGND TXD7d TXD6d VDIGCd TXD4a TXD3a TXD2a TXD1a M DGND TXENd DVDD TXERd TXENa TXD7a TXD6a TXD5a N RESETN TEST FRSYN1 FRSYN0 MDIO TXERa VDIGCa DGND P ANTEST0 ANTEST1 GTXMc AVDD AVDD VRXMb MDC VDIGCb R REFP VTXMc VRXMc GTXMd VTXMb TRS TCK TMS T REFN GRXMc VTXMd VRXMd GRXMa GTXMb TDI TDO U GRXMd ENCODE FRAME AVDD LOSd GRXDd AVDD TXNd TXPd GTXDc VTXDb TXNa TXPa AVDD GRXDa GTXMa AVDD VRXMa LBEN GRXMb V AGND AVDD AVDD SER8_10 LOSc POLd GRXDc GTXDd TXNc TXPc TXPb TXNb GTXDa GRXDb VRXDa LOSb POLa AVDD AVDD AGND W AGND AVDD AVDD VRXDd RXNd RXPd VTXDd GFS3 VTXDc GFS1 VFS2 GTXDb VTXDa VRXDb RXNa RXPa VTXMa AVDD AVDD AGND Y AGND AGND AGND POLc VRXDc RXNc RXPc AGND VFS3 VFS1 AGND AGND GFS2 RXNb RXPb POLb LOSa AGND AGND AGND Document #: 38-02019 Rev. *C Page 4 of 34 PRELIMINARY Pin Configuration (Bottom View) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 CYP32G0401DX 4 3 2 1 DGND DGND DGND RXCLKb RXD7b RCLKINb TXD4b DGND GTXCLKb TCLKOUT DGND DGND TXD5c GTXCLKc RXCLKc RXD2c RCLKINc DGND DGND DGND A DGND DVDD DVDD RXD4b RXD6b RXDVb TXD5b TXD2b TXD0b VDIGCc TXENc TXD7c TXD3c TXD1c RXD0c RXD3c RXD5c DVDD DVDD DGND B DGND DVDD DVDD RXD3b RXD5b TXENb TXD7b TXD3b TXD1b TSYNC TXERc TXD6c TXD2c COLc RXD1c RXD4c RXD7c DVDD DVDD DGND C RXD0b RXD1b RXD2b DVDD RXERb TXERb DVDD TXD6b GDIGCb GDIGCc DVDD TXD4c TXD0c DVDD CRSc RXD6c DVDD RXERc RXDVc OOFd D RXCLKa OOFa CRSb COLb OOFc RXDVd RXD7d RXCLKd E RXD7a RXERa RXDVa OOFb RXERd RXD6d RXD5d RXD4d F RXD3a RXD4a RXD6a GDIGCa GDIGCd RXD3d RXD2d RCLKINd G RCLKINa CRSa RXD2a RXD5a COLd RXD1d RXD0d DGND H DGND COLa RXD0a RXD1a CRSd TXD0d TXD1d GTXCLKd J DGND GTXCLKa TXD0a DVDD TXD2d TXD3d TXD4d TXD5d K TXD1a TXD2a TXD3a TXD4a VDIGCd TXD6d TXD7d DGND L TXD5a TXD6a TXD7a TXENa TXERd DVDD TXENd DGND M DGND VDIGCa TXERa MDIO FRSYN0 FRSYN1 TEST RESETN N VDIGCb MDC VRXMb AVDD AVDD GTXMc ANTEST1 ANTEST0 P TMS TCK TRS VTXMb GTXMd VRXMc VTXMc REFP R TDO TDI GTXMb GRXMa VRXMd VTXMd GRXMc REFN T GRXMb LBEN VRXMa AVDD GTXMa GRXDa AVDD TXPa TXNa VTXDb GTXDc TXPd TXNd AVDD GRXDd LOSd AVDD FRAME ENCODE GRXMd U AGND AVDD AVDD POLa LOSb VRXDa GRXDb GTXDa TXNb TXPb TXPc TXNc GTXDd GRXDc POLd LOSc SER8_10 AVDD AVDD AGND V AGND AVDD AVDD VTXMa RXPa RXNa VRXDb VTXDa GTXDb VFS2 GFS1 VTXDc GFS3 VTXDd RXPd RXNd VRXDd AVDD AVDD AGND W AGND AGND AGND LOSa POLb RXPb RXNb GFS2 AGND AGND VFS1 VFS3 AGND RXPc RXNc VRXDc POLc AGND AGND AGND Y Document #: 38-02019 Rev. *C Page 5 of 34 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +100C Supply Voltage to Ground Potential ............... -0.5V to +3.0V DC Voltage Applied on Any Pin with Respect to Ground (with VDD in Normal Operating Range)....-0.5V to VDD+0.5V CYP32G0401DX Static Discharge Voltage.................................................> 500 V (per JEDEC) Latch-Up Current...........................................................> 200 mA Operating Range Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD +2.5V 5% +2.5V 5% Pin Descriptions CYP32G0401DX Transmitter Pins (53)[1] Pin K18, L20 L19, L18 L17, M20 M19, M18 Name TXD0a, TXD1a TXD2a, TXD3a TXD4a, TXD5a TXD6a, TXD7a Level SSTL_2 I/O inputs Description Channel a transmit data in. The transmit data TXDa[7:0] are clocked into the Phase Align FIFO on the rising edge of the GTXCLKa signal. The data are read out of the Phase Align FIFO with TCLKOUT. The phase of GTXCLKa may differ from that of TCLKOUT by any amount. In MODE 1[1] the frequency of GTXCLKa may differ from that of TCLKOUT by up to 200 ppm. Channel a transmit enable (TXENa) in MODE 1 Channel a transmit data bit 8 (TXD8a) in MODE 2 Not used in MODE 3 (Suggest user drive to zero) Not used in MODE 4 (Suggest user drive to zero) Channel a transmit error (TXERa) in MODE 1 Channel a transmit data bit 9 (TXD9a) in MODE 2 Channel a transmit code-group select (TXKa) in MODE 3 Not used in MODE 4 (Suggest user drive to zero) Channel a transmit clock. The rising edge of GTXCLKa clocks the input data into the Phase Align FIFO. Channel a differential serial data transmit. TXPa is the positive differential output pin of the channel a Line Driver. The TXPa and TXNa look like a differential amplifier with each of the output drains connected to VDD through a 50 resistor. Channel a differential serial data transmit. TXNa is the negative differential output pin of the channel a Line Driver. The TXPa and TXNa look like a differential amplifier with each of the output drains connected to VDD through a 50 resistor. Channel b transmit data in. The transmit data TXDb[7:0] are clocked into the Phase Align FIFO on the rising edge of the GTXCLKb signal. The data are read out of the Phase Align FIFO with TCLKOUT. The phase of GTXCLKb may differ from that of TCLKOUT by any amount. In MODE 1 the frequency of GTXCLKb may differ from that of TCLKOUT by up to 200 ppm. Channel b transmit enable (TXENb) in MODE 1 Channel b transmit data bit 8 (TXD8b) in MODE 2 Not used in MODE 3 (Suggest user drive to zero) Not used in MODE 4 (Suggest user drive to zero) Channel b transmit error (TXERb) in MODE 1 Channel b transmit data bit 9 (TXD9b) in MODE 2 Channel b transmit code-group Select (TXKb) in MODE 3 Not used in MODE 4 (Suggest user drive to zero) Channel b transmit clock. The rising edge of GTXCLKb clocks the input data into the Phase Align FIFO. M17 TXENa SSTL_2 input N18 TXERa SSTL_2 input K19 U13 GTXCLKa TXPa SSTL_2 CML input output U12 TXNa CML output B12, C12 B13, C13 A14, B14 D13, C14 TXD0b, TXD1b TXD2b, TXD3b TXD4b, TXD5b TXD6b, TXD7b SSTL_2 inputs C15 TXENb SSTL_2 input D15 TXERb SSTL_2 input A12 GTXCLKb SSTL_2 input Note: 1. Transmitter pins are MODE-dependent where indicated. See Table 1 for defined MODES of operation. Document #: 38-02019 Rev. *C Page 6 of 34 PRELIMINARY Pin Descriptions CYP32G0401DX Transmitter Pins (53)[1] (continued) Pin V11 Name TXPb Level CML I/O output Description CYP32G0401DX Channel b differential Serial Data Transmit. TXPb is the positive differential output pin of the channel b Line Driver. The TXPb and TXNb look like a differential amplifier with each of the output drains connected to VDD through a 50 resistor. Channel b differential serial data transmit. TXNb is the negative differential output pin of the channel b Line Driver. The TXPb and TXNb look like a differential amplifier with each of the output drains connected to VDD through a 50 resistor. Channel c transmit data in. The transmit data TXDc[7:0] are clocked into the Phase Align FIFO on the rising edge of the GTXCLKc signal. The data are read out of the Phase Align FIFO with TCLKOUT. The phase of GTXCLKc may differ from that of TCLKOUT by any amount. In MODE 1 the frequency of GTXCLKc may differ from that of TCLKOUT by up to 200 ppm. Channel c transmit enable (TXENc) in MODE 1 Channel c transmit data bit 8 (TXD8c) in MODE 2 Not used in MODE 3 (Suggest user drive to zero) Not used in MODE 4 (Suggest user drive to zero) Channel c transmit error (TXERc) in MODE 1 Channel c transmit data bit 9 (TXD9c) in MODE 2 Channel c transmit code-group select (TXKc) in MODE 3 Not used in MODE 4 (Suggest user drive to zero) Channel c transmit clock.The rising edge of GTXCLKc clocks the input data into the Phase Align FIFO. Channel c differential serial data transmit. TXPc is the positive differential output pin of the channel c Line Driver. The TXPc and TXNc look like a differential amplifier with each of the output drains connected to VDD through a 50 resistor. Channel c differential serial data transmit. TXNc is the negative differential output pin of the channel c Line Driver. The TXPc and TXNc look like a differential amplifier with each of the output drains connected to VDD through a 50 resistor. Channel d transmit data in. The transmit data TXDd[7:0] are clocked into the Phase Align FIFO on the rising edge of the GTXCLKd signal. The data are read out of the Phase Align FIFO with TCLKOUT. The phase of GTXCLKd may differ from that of TCLKOUT by any amount. In MODE 1 the frequency of GTXCLKd may differ from that of TCLKOUT by up to 200 ppm. Channel d transmit enable (TXENd) in MODE 1 Channel d transmit data bit 8 (TXD8d) in MODE 2 Not used in MODE 3 (Suggest user drive to zero) Not used in MODE 4 (Suggest user drive to zero) Channel d transmit error (TXERd) in MODE 1 Channel d transmit data bit 9 (TXD9d) in MODE 2 Channel d transmit code-group select (TXKd) in MODE 3 Not used in MODE 4 (Suggest user drive to zero) Channel d transmit clock. The rising edge of GTXCLKd clocks the input data into the Phase Align FIFO. Channel d differential serial data transmit. TXPd is the positive differential output pin of the channel d Line Driver. The TXPd and TXNd look like a differential amplifier with each of the output drains connected to VDD through a 50 resistor. V12 TXNb CML output D8, B7 C8, B8 D9, A8 C9, B9 TXD0c, TXD1c TXD2c, TXD3c TXD4c, TXD5c TXD6c, TXD7c SSTL_2 inputs B10 TXENc SSTL_2 input C10 TXERc SSTL_2 input A7 V10 GTXCLKc TXPc SSTL_2 CML input output V9 TXNc CML output J3, J2 K4, K3 K2, K1 L3, L2 TXD0d, TXD1d TXD2d, TXD3d TXD4d, TXD5d TXD6d, TXD7d SSTL_2 inputs M2 TXENd SSTL_2 input M4 TXERd SSTL_2 input J1 U9 GTXCLKd TXPd SSTL_2 CML input output Document #: 38-02019 Rev. *C Page 7 of 34 PRELIMINARY Pin Descriptions CYP32G0401DX Transmitter Pins (53)[1] (continued) Pin U8 Name TXNd Level CML I/O output Description CYP32G0401DX Channel d differential serial data transmit. TXNd is the negative differential output pin of the channel d Line Driver. The TXPd and TXNd look like a differential amplifier with each of the output drains connected to VDD through a 50 resistor. Reference transmit clock output. TCLKOUT is the word clock signal used to clock data out of the Transmit Phase Align FIFOs of all four channels. TCLKOUT is derived directly from the Frequency Synthesizer output. A11 TCLKOUT SSTL_2 output CYP32G0401DX Receiver Pins (76)[2] Pin J18, J17 H18, G20 G19, H17 G18, F20 F19 Name RXD0a, RXD1a RXD2a, RXD3a RXD4a, RXD5a RXD6a, RXD7a RXERa Level SSTL_2 I/O outputs Description Channel a receive data. The receive data RXDa[7:0] are clocked out of the Elasticity FIFO by RCLKINa. SSTL_2 output Channel a receive error (RXERa) in MODE 1[2] Channel a receive data bit9 (RXD9a) in MODE 2 Channel a receive invalid character flag (ERRa) in MODE 3 Not used in MODE 4 Channel a receive data valid (RXDVa) in MODE 1 Channel a receive data bit8 (RXD8a) in MODE 2 Channel a receive code-group select (RXKa) in MODE 3 Not used in MODE 4 Channel a receive carrier sense indicate (CRSa) in MODE 1 Not used in MODE 2 Channel a receive idle code (IDLEa) in MODE 3 Channel a receive frame pulse flag (FRPa) in MODE 4 Channel a receive collision indicate (COLa) in MODE 1 Not used in MODE 2 Channel a receive invalid character flag (ERRa) in MODE 3 Not used in MODE 4 Channel a receive clock output reference. The RXCLKa pin outputs either a buffered RCLKINa, or the recovered clock. This is determined by the status of LBEN on the rising edge of RESETN as follows: LBEN = 0 selects the buffered RCLKINa; LBEN = 1 selects the recovered clock. Not used in MODE 1 Not used in MODE 2 Not used in MODE 3 Channel a OOF indicate in MODE 4 Channel a receive Elasticity FIFO output clock. RCLKINa clocks the receive data RXDa[7:0], RXDVa, and RXERa out of the channel a Elasticity FIFO. Channel a serial receive data, ext. ac coupled, int. bias. RXPa is the positive differential input pin of the channel a Line Receiver. The RXPa and RXNa look like a differential amplifier with each of the input pins connected to VDD/2 through a 150 resistor. When inputs are differentially terminated with a 150 resistor, the line termination is nominally 100. See Figure 6. F18 RXDVa SSTL_2 output H19 CRSa SSTL_2 output J19 COLa SSTL_2 output E20 RXCLKa SSTL_2 output E19 OOFa SSTL_2 input H20 RCLKINa SSTL_2 input W16 RXPa CML input Note: 2. Receiver pins are MODE-dependent where indicated. See Table 1 for defined MODES of operation. Document #: 38-02019 Rev. *C Page 8 of 34 PRELIMINARY CYP32G0401DX Receiver Pins (76)[2] (continued) Pin W15 Name RXNa Level CML I/O input Description CYP32G0401DX Channel a serial receive data, ext. ac coupled, int. bias. RXNa is the negative differential input pin of the channel a Line Receiver. The RXPa and RXNa look like a differential amplifier with each of the input pins connected to VDD/2 through a 150 resistor. When inputs are differentially terminated with a 150 resistor, the line termination is nominally 100. See Figure 6. Channel a receive loss of signal indicate. The signal input on the LOSa pin may come from a fiber module and indicates if there is a Loss of Signal (LOS) condition. If a LOS condition occurs, the data input is squelched and no data is sent to the data recovery block. When no data edges are present at the inputs to the clock recovery Digital Phase-Locked Loop (DPLL), its output frequency will be locked to the frequency of the transmit Frequency Synthesizer. The polarity of the LOSa signal is controlled by the POLa pin as shown in Table 4. Channel a receive loss of signal polarity. The POLa pin controls the polarity of the LOSa signal as shown in Table 4. Channel b receive data. The receive data RXDb[7:0] are clocked out of the Elasticity FIFO by RCLKINb. Y17 LOSa LVPECL input V17 D20, D19 D18, C17 B17, C16 B16, A16 D16 POLa RXD0b, RXD1b RXD2b, RXD3b RXD4b, RXD5b RXD6b, RXD7b RXERb SSTL_2 SSTL_2 input outputs SSTL_2 output Channel b receive error (RXERb) in MODE 1 Channel b receive data bit9 (RXD9b) in MODE 2 Channel b receive invalid character flag (ERRb) in MODE 3 Not used in MODE 4 Channel b receive data valid (RXDVb) in MODE 1 Channel b receive data bit8 (RXD8b) in MODE 2 Channel B receive code-group select (RXKb) in MODE 3 Not used in MODE 4 Channel b receive carrier sense indicate (CRSb) in MODE 1 Not used in MODE 2 Channel b receive idle code (IDLEb) in MODE 3 Channel b receive frame pulse flag (FRPb) in MODE 4 Channel b receive collision indicate (COLb) in MODE 1 Not used in MODE 2 Channel b receive invalid character flag (ERRb) in MODE 3 Not used in MODE 4 Channel b receive clock output reference. The RXCLKb pin outputs either a buffered RCLKINb, or the recovered clock. This is determined by the status of LBEN on the rising edge of RESETN as follows: LBEN = 0 selects the buffered RCLKINb; LBEN = 1 selects the recovered clock. Not used in MODE 1 Not used in MODE 2 Not used in MODE 3 Channel b OOF indicate in MODE 4 Channel b receive Elasticity FIFO output clock. RCLKINb clocks the receive data RXDb[7:0], RXDVb, and RXERb out of the channel b Elasticity FIFO. Channel b serial receive data, ext. ac coupled, int. bias. RXPb is the positive differential input pin of the channel b Line Receiver. The RXPb and RXNb look like a differential amplifier with each of the input pins connected to VDD/2 through a 150 resistor. When inputs are differentially terminated with a 150 resistor, the line termination is nominally 100. See Figure 6. B15 RXDVb SSTL_2 output E18 CRSb SSTL_2 output E17 COLb SSTL_2 output A17 RXCLKb SSTL_2 output F17 OOFb SSTL_2 input A15 RCLKINb SSTL_2 input Y15 RXPb CML input Document #: 38-02019 Rev. *C Page 9 of 34 PRELIMINARY CYP32G0401DX Receiver Pins (76)[2] (continued) Pin Y14 Name RXNb Level CML I/O input Description CYP32G0401DX Channel b serial receive data, ext. ac coupled, int. bias. RXNb is the negative differential input pin of the channel b Line Receiver. The RXPb and RXNb look like a differential amplifier with each of the input pins connected to VDD/2 through a 150 resistor. When inputs are differentially terminated with a 150 resistor, the line termination is nominally 100. See Figure 6. Channel b receive loss of signal indicate. The signal input on the LOSb pin may come from a fiber module and indicates if there is a Loss of Signal (LOS) condition. If a LOS condition occurs, the data input is squelched and no data is sent to the data recovery block. When no data edges are present at the inputs to the clock recovery Digital Phase-Locked Loop (DPLL), its output frequency will be locked to the frequency of the transmit Frequency Synthesizer. The polarity of the LOSb signal is controlled by the POLb pin as shown in Table 4. Channel b receive loss of signal polarity. The POLb pin controls the polarity of the LOSb signal as shown in Table 4. Channel c receive data. The receive data RXDc[7:0] are clocked out of the Elasticity FIFO by RCLKINc. V16 LOSb LVPECL input Y16 B6, C6 A5, B5 C5, B4 D5, C4 D3 POLb RXD0c, RXD1c RXD2c, RXD3c RXD4c, RXD5c RXD6c, RXD7c RXERc SSTL_2 SSTL_2 input outputs SSTL_2 output Channel c receive error (RXERc) in MODE 1 Channel c receive data bit9 (RXD9c) in MODE 2 Channel c receive invalid character flag (ERRc) in MODE 3 Not used in MODE 4 Channel c receive data valid (RXDVc) in MODE 1 Channel c receive data bit8 (RXD8c) in MODE 2 Channel c receive code-group select (RXKc) in MODE 3 Not used in MODE 4 Channel c receive carrier sense indicate (CRSc) in MODE 1 Not used in MODE 2 Channel c receive idle code (IDLEc) in MODE 3 Channel c receive frame pulse flag (FRPc) in MODE 4 Channel c receive collision indicate (COLc) in MODE 1 Not used in MODE 2 Channel c receive invalid character flag (ERRc) in MODE 3 Not used in MODE 4 Channel c receive clock output reference. The RXCLKc pin outputs either a buffered RCLKINc, or the recovered clock. This is determined by the status of LBEN on the rising edge of RESETN as follows: LBEN = 0 selects the buffered RCLKINc; LBEN = 1 selects the recovered clock. Not used in MODE 1 Not used in MODE 2 Not used in MODE 3 Channel c OOF indicate in MODE 4 Channel c receive Elasticity FIFO output clock. RCLKINc clocks the receive data RXDc[7:0], RXDVc, and RXERc out of the channel c Elasticity FIFO. Channel c serial receive data, ext. ac coupled, int. bias. RXPc is the positive differential input pin of the channel c Line Receiver. The RXPc and RXNc look like a differential amplifier with each of the input pins connected to VDD/2 through a 150 resistor. When inputs are differentially terminated with a 150 resistor, the line termination is nominally 100. See Figure 6. D2 RXDVc SSTL_2 output D6 CRSc SSTL_2 output C7 COLc SSTL_2 output A6 RXCLKc SSTL_2 output E4 OOFc SSTL_2 input A4 RCLKINc SSTL_2 input Y7 RXPc CML input Document #: 38-02019 Rev. *C Page 10 of 34 PRELIMINARY CYP32G0401DX Receiver Pins (76)[2] (continued) Pin Y6 Name RXNc Level CML I/O input Description CYP32G0401DX Channel c serial receive data, ext. ac coupled, int. bias. RXNc is the negative differential input pin of the channel c Line Receiver. The RXPc and RXNc look like a differential amplifier with each of the input pins connected to VDD/2 through a 150 resistor. When inputs are differentially terminated with a 150 resistor, the line termination is nominally 100. See Figure 6. Channel c receive loss of signal indicate. The signal input on the LOSc pin may come from a fiber module and indicates if there is a Loss of Signal (LOS) condition. If a LOS condition occurs, the data input is squelched and no data is sent to the data recovery block. When no data edges are present at the inputs to the clock recovery Digital Phase-Locked Loop (DPLL), its output frequency will be locked to the frequency of the transmit Frequency Synthesizer. The polarity of the LOSc signal is controlled by the POLc pin as shown in Table 4. Channel c receive loss of signal polarity. The POLc pin controls the polarity of the LOSc signal as shown in Table 4. Channel d receive data. The receive data RXDd[7:0] are clocked out of the Elasticity FIFO by RCLKINd. V5 LOSc LVPECL input Y4 H2, H3 G2, G3 F1, F2 F3, E2 F4 POLc RXD0d, RXD1d RXD2d, RXD3d RXD4d, RXD5d RXD6d, RXD7d RXERd SSTL_2 SSTL_2 input outputs SSTL_2 output Channel d receive error (RXERd) in MODE 1 Channel d receive data bit9 (RXD9d) in MODE 2 Channel d receive invalid character flag (ERRd) in MODE 3 Not used in MODE 4 Channel d receive data valid (RXDVd) in MODE 1 Channel d receive data bit8 (RXD8d) in MODE 2 Channel d receive code-group select (RXKd) in MODE 3 Not used in MODE 4 Channel d receive carrier sense indicate (CRSd) in MODE 1 Not used in MODE 2 Channel d receive idle code (IDLEd) in MODE 3 Channel d receive frame pulse flag (FRPd) in MODE 4 Channel d receive collision indicate (COLd) in MODE 1 Not used in MODE 2 Channel d receive invalid character flag (ERRd) in MODE 3 Not used in MODE 4 Channel d receive clock output reference. The RXCLKd pin outputs either a buffered RCLKINd, or the recovered clock. This is determined by the status of LBEN on the rising edge of RESETN as follows: LBEN = 0 selects the buffered RCLKINd; LBEN = 1 selects the recovered clock. Not used in MODE 1 Not used in MODE 2 Not used in MODE 3 Channel d OOF indicate in MODE 4 Channel d receive Elasticity FIFO output clock. RCLKINd clocks the receive data RXDd[7:0], RXDVd, and RXERd out of the channel d Elasticity FIFO. Channel d serial receive data, ext. ac coupled, int. bias. RXPd is the positive differential input pin of the channel d Line Receiver. The RXPd and RXNd look like a differential amplifier with each of the input pins connected to VDD/2 through a 150 resistor. When inputs are differentially terminated with a 150 resistor, the line termination is nominally 100. See Figure 6. E3 RXDVd SSTL_2 output J4 CRSd SSTL_2 output H4 COLd SSTL_2 output E1 RXCLKd SSTL_2 output D1 OOFd SSTL_2 input G1 RCLKINd SSTL_2 input W6 RXPd CML input Document #: 38-02019 Rev. *C Page 11 of 34 PRELIMINARY CYP32G0401DX Receiver Pins (76)[2] (continued) Pin W5 Name RXNd Level CML I/O input Description CYP32G0401DX Channel d serial receive data, ext. ac coupled, int. bias. RXNd is the negative differential input pin of the channel d Line Receiver. The RXPd and RXNd look like a differential amplifier with each of the input pins connected to VDD/2 through a 150 resistor. When inputs are differentially terminated with a 150 resistor, the line termination is nominally 100. See Figure 6. Channel d receive loss of signal indicate. The signal input on the LOSd pin may come from a fiber module and indicates if there is a Loss of Signal (LOS) condition. If a LOS condition occurs, the data input is squelched and no data is sent to the data recovery block. When no data edges are present at the inputs to the clock recovery Digital Phase-Locked Loop (DPLL), its output frequency will be locked to the frequency of the transmit Frequency Synthesizer. The polarity of the LOSd signal is controlled by the POLd pin as shown in Table 4. Channel d receive loss of signal polarity. The POLd pin controls the polarity of the LOSd signal as shown in Table 4. U5 LOSd LVPECL input V6 POLd SSTL_2 input CYP32G0401DX Control pins (11)[3] Pin N1 Name RESETN Level SSTL_2 I/O Bidir Description Chip global reset (active LOW bidirectional pull down). The RESETN pin reflects the operation of the Power On Reset (POR) circuit. When POR is active, RESETN is driven LOW. When POR is inactive, RESETN is three-stated and an internal pull-up resistor (approximately 50 k) establishes the inactive (HIGH) state. The RESETN pin may also be driven from an external device in order to re-initialize the chip regardless of the internal operating state and regardless of the state of POR. In this case RESETN must be driven LOW for a minimum of two cycles of the reference clock (REFP, REFN), though no other timing relationship between RESETN and the reference clock need exist. Management Interface Data Clock Management Interface Data Input/Output Frequency Synthesizer PLL ratio select. The FRSYN0 and FRSYN1 pins, together with the SER8_10 pin, select from the allowable reference clock frequency ranges for input to the frequency synthesizer. See Table 2. 8-bit (SER8_10 = 1), 10-bit (SER8_10 = 0) data select.[3] The parallel-to-serial and serial-to-parallel converters operate in two modes, eight-bit and ten-bit, under the control of the SER8_10 pin, as shown inTable 3. The 8-bit/10-bit selection made using the SER8_10 pin will also affect the choice of reference clock frequency range made using the FRSYN0 and FRSYN1 pins, as shown in Table 2. Encode select.[3] The 8B/10B encode and decode functions are enabled when ENCODE = 1. The encoder translates the 8-bit input byte to a 10-bit symbol for transmit, and the decoder translates the received 10-bit symbol to the 8-bit byte originally encoded at the other end. Both encode and decode functions are bypassed when ENCODE = 0. P19 N17 N4 N3 MDC MDIO FRSYN0 FRSYN1 SSTL_2 SSTL_2 SSTL_2 input Bidir input V4 SER8_10 SSTL_2 input U2 ENCODE SSTL_2 input Note: 3. The control pins SER8_10, ENCODE and FRAME together select the operating MODE. See Table 1 for defined operating MODES. Document #: 38-02019 Rev. *C Page 12 of 34 PRELIMINARY CYP32G0401DX Control pins (11)[3] (continued) Pin U3 Name FRAME Level SSTL_2 I/O input Description CYP32G0401DX Frame select.[3] The Ethernet PCS functions are enabled when FRAME=1. This performs Ethernet PCS functions using the IEEE802.3z ordered set state machine (Section 36.2.5.2.1 and Figures 36-5 and 36-6) during transmit, and the receive and synchronization state machines (Section 36.2.5.2.2 and Figures 367a, 36-7b, 36-8, and 36-9) during receive. Loop back enable. When loop back is enabled (LBEN = 1) both the high-speed line side data and the byte input data are looped back. The parallel input data (TXD[7:0], TXEN, TXER) are looped back to the receive side parallel data (RXD[7:0], RXDV, RXER), and the line-received data (RXP and RXN) are looped back and sent to the line driver (TXP and TXN). In MODE 1 the transmit driver (TXP, TXN) is disabled, as required in IEEE802.3 Section 22.2.4.1.2. Note: LBEN is logically ORed with bit 0.14 of the control register. Differential Frequency Synthesizer clock input, externally ac coupled, internally biased. REFP is the positive differential input pin for the reference clock (REFCLK) used by the frequency synthesizer. The REFP and REFN look like a differential amplifier with each of the input pins connected to 0.75xVDD through a 150 resistor. See Table 7. Differential Frequency Synthesizer clock input, externally ac coupled, internally biased. REFN is the negative differential input pin for the reference clock (REFCLK) used by the frequency synthesizer. The REFP and REFN look like a differential amplifier with each of the input pins connected to 0.75xVDD through a 150 resistor. See Table 7. U19 LBEN SSTL_2 input R1 REFP CML input T1 REFN CML input CYP32G0401DX Analog Power Pins (65) Pin Y10 W11 Y9 W10 Y13 W8 W13 W17 V13 U16 U11 R17 W12 T18 W9 R2 U10 P3 W7 T3 V8 Name VFS1 VFS2 VFS3 GFS1 GFS2 GFS3 VTXDa VTXMa GTXDa GTXMa VTXDb VTXMb GTXDb GTXMb VTXDc VTXMc GTXDc GTXMc VTXDd VTXMd GTXDd Function Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Description Frequency Synthesizer PLL VDD1 Frequency Synthesizer PLL VDD2 Frequency Synthesizer PLL VDD3 Frequency Synthesizer PLL GND1 Frequency Synthesizer PLL GND2 Frequency Synthesizer PLL GND3 Channel a transmit VDD1 Channel a transmit VDD2 Channel a transmit GND1 Channel a transmit GND2 Channel b transmit VDD1 Channel b transmit VDD2 Channel b transmit GND1 Channel b transmit GND2 Channel c transmit VDD1 Channel c transmit VDD2 Channel c transmit GND1 Channel c transmit GND2 Channel d transmit VDD1 Channel d transmit VDD2 Channel d transmit GND1 Page 13 of 34 Document #: 38-02019 Rev. *C PRELIMINARY CYP32G0401DX Analog Power Pins (65) (continued) Pin R4 V15 U18 U15 T17 W14 P18 V14 U20 Y5 R3 V7 T2 W4 T4 U6 U1 P4 P17 U4 U7 U14 U17 V2 V3 V18 V19 W2 W3 W18 W19 V1 V20 W1 W20 Y1 Y2 Y3 Y8 Y11 Y12 Y18 Y19 Y20 Name GTXMd VRXDa VRXMa GRXDa GRXMa VRXDb VRXMb GRXDb GRXMb VRXDc VRXMc GRXDc GRXMc VRXDd VRXMd GRXDd GRXMd AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND Function Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Analog Power Description Channel d transmit GND2 Channel a receive VDD1 Channel a receive VDD2 Channel a receive GND1 Channel a receive GND2 Channel b receive VDD1 Channel b receive VDD2 Channel b receive GND1 Channel b receive GND2 Channel c receive VDD1 Channel c receive VDD2 Channel c receive GND1 Channel c receive GND2 Channel d receive VDD1 Channel d receive VDD2 Channel d receive GND1 Channel d receive GND2 General Analog VDD General Analog VDD General Analog VDD General Analog VDD General Analog VDD General Analog VDD General Analog VDD General Analog VDD General Analog VDD General Analog VDD General Analog VDD General Analog VDD General Analog VDD General Analog VDD General Analog GND General Analog GND General Analog GND General Analog GND General Analog GND General Analog GND General Analog GND General Analog GND General Analog GND General Analog GND General Analog GND General Analog GND General Analog GND CYP32G0401DX Document #: 38-02019 Rev. *C Page 14 of 34 PRELIMINARY CYP32G0401DX Digital Power Pins (42) Pin N19 P20 B11 L4 G17 D12 D11 G4 B2 B3 B18 B19 C2 C3 C18 C19 D4 D7 D10 D14 D17 K17 M3 A1 A2 A3 A9 A10 A13 A18 A19 A20 B1 B20 C1 C20 H1 J20 K20 L1 M1 N20 Name VDIGCa VDIGCb VDIGCc VDIGCd GDIGCa GDIGCb GDIGCc GDIGCd DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND Function Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Digital Power Description Channel a Core VDD Channel b Core VDD Channel c Core VDD Channel d Core VDD Channel a Core GND Channel b Core GND Channel c Core GND Channel d Core GND Digital IO Ring VDD Digital IO Ring VDD Digital IO Ring VDD Digital IO Ring VDD Digital IO Ring VDD Digital IO Ring VDD Digital IO Ring VDD Digital IO Ring VDD Digital IO Ring VDD Digital IO Ring VDD Digital IO Ring VDD Digital IO Ring VDD Digital IO Ring VDD Digital IO Ring VDD Digital IO Ring VDD Digital IO Ring GND Digital IO Ring GND Digital IO Ring GND Digital IO Ring GND Digital IO Ring GND Digital IO Ring GND Digital IO Ring GND Digital IO Ring GND Digital IO Ring GND Digital IO Ring GND Digital IO Ring GND Digital IO Ring GND Digital IO Ring GND Digital IO Ring GND Digital IO Ring GND Digital IO Ring GND Digital IO Ring GND Digital IO Ring GND Digital IO Ring GND CYP32G0401DX Document #: 38-02019 Rev. *C Page 15 of 34 PRELIMINARY CYP32G0401DX CYP32G0401DX Cypress Test Pins (6) - User Connect to Ground Pin R20 R19 T19 R18 N2 C11 Name TMS TCK TDI TRS TEST TSYNC Level I/O Description User Connect to Ground User Connect to Ground User Connect to Ground User Connect to Ground User Connect to Ground User Connect to Ground CYP32G0401DX Cypress Special Pins (3) - N/C Pin T20 P1 P2 Name TDO ANTEST0 ANTEST1 Level I/O Description No Connection No Connection Document #: 38-02019 Rev. *C Page 16 of 34 PRELIMINARY CYP32G0401DX HOTLink-III Operation The CYP32G0401DX is a highly configurable device designed to support reliable transfer of large quantities of data, using high-speed serial links. This device supports four single-byte or single-character channels. CYP32G0401DX and Ethernet PCS functions. (SER8_10 = 0, ENCODE = 1, FRAME = 1). MODE 2 - 10-bit SERDES (no encoding/decoding; no framing) The transmit side accepts data in the form of 10-bit words at up to 312.5 Mwps, and serializes them into a bit stream transmitting at up to 3.125 Gbps. The receive side deserializes the data. No encoding/decoding or framing functions are performed. (SER8_10 = 0, ENCODE = 0, FRAME = 0). MODE 3 - 10-bit SERDES (8B/10B encoding/decoding; COMMA framing) The transmit side accepts data in the form of 8-bit bytes at up to 312.5 MBps, performs 8B/10B encoding, and serializes the encoded words into a bit stream transmitting at up to 3.125 Gbps. The receive side deserializes the data, and performs COMMA framing and 8B/10B decoding. (SER8_10 = 0, ENCODE = 1, FRAME = 0). MODE 4 - 8-bit SERDES (no encoding/decoding; A1/A2 framing) The transmit side accepts data in the form of 8-bit bytes at up to 350 MBps, and serializes them into a bit stream transmitting at up to 2.8 Gbps. The receive side deserializes the data and performs SONET/SDH A1/A2 framing. (SER8_10 = 1, ENCODE = 0, FRAME = 0). Table 1. CYP32G0401DX Operating Mode[4] SER ENMODE 8_10 CODE FRAME APPLICATION 10 bit SERDES, 8B/10B 1 0 1 1 encoding/decoding, COMMA framing, and PCS functions 10 bit SERDES, 2 0 0 0 no encoding/decoding, and no framing 10 bit SERDES, 8B/10B 3 0 1 0 encoding/decoding, and COMMA framing 8 bit SERDES, 4 1 0 0 no encoding/decoding, and A1/A2 framing Note: 4. Choose from four defined operating modes by setting variables SER8_10, ENCODE and FRAME. Selected mode applies to all four channels. General Description The CYP32G0401DX is a fully integrated quad transceiver device capable of operating at serial rates up to 3.125 Gbps per channel. The CYP32G0401DX has four operating modes: MODE 1 - 10-bit SERDES (Ethernet PCS functions; 8B/10B encoding/decoding; COMMA framing), MODE 2 - 10-bit SERDES (no encoding/decoding; no framing), MODE 3 - 10-bit SERDES (8B/10B encoding/decoding; COMMA framing), and MODE 4 - 8-bit SERDES (no encoding/decoding; A1/A2 framing). It performs the 8B/10B encode and decode functions compatible with the 10G Ethernet and InfiniBand physical layer, parallel-to-serial conversion, serial-to-parallel conversion, and clock recovery functions for use in LAN and WAN applications. The Multi-Gigabit Multi-Mode versatility of the CYP32G0401DX was designed for backplane applications for WAN, LAN, WIN, and storage networks' switches and routers as well as for InfiniBand and XAUI 10G Ethernet port applications. Functional Description Overview Figure 4 shows a block diagram of a typical four-channel application. The transceiver has four defined modes of operation as shown in Table 1. CYP32G0401DX FIBER P A R A L L E L D A T A Tx a Rx Tx b Rx Tx Rx Tx Rx S E R I A L D A T A c d Architecture Overview Figure 3 is a block diagram showing one of the four multi-gigabit transceiver channels contained within the CYP32G0401DX. Also shown are the internal Management Interface and Frequency Synthesizer blocks, which are common to all channels. Pin names are written in uppercase letters, with lowercase suffixes (a, b, c, d) applied later, as needed, to distinguish among the four channels. In generic cases, the lowercase suffix `x' will be used to denote channels a, b, c, and d. Frequency Synthesizer A Frequency Synthesizer PLL generates the low jitter transmit clock. This clock is derived from a low jitter reference frequency applied differentially at pins REFP and REFN. The output Page 17 of 34 Figure 4. Typical CYP32G0401DX Application Block Diagram MODE 1 - 10-bit SERDES (Ethernet PCS functions; 8B/10B encoding/decoding; COMMA framing) The transmit side accepts data in the form of 8-bit bytes at up to 312.5 MBps, performs Ethernet PCS functions using the IEEE802.3z ordered set state machine, 8B/10B encoding and serialization of the encoded words into a serial bit stream transmitting at up to 3.125 Gbps. The receive side deserializes the data and performs COMMA framing, 8B/10B decoding, Document #: 38-02019 Rev. *C PRELIMINARY frequency of the synthesizer is set to provide data output rates between 2.488 Gbps and 3.125 Gbps, and is a multiple of the reference clock frequency. Allowable reference clock frequency ranges are selected by the SER8_10 and FRSYN[1:0] signals, as shown in Table 2. Table 2. Frequency Synthesizer Selectable Input Frequency Range Selected Input Reference Data Frequency Output Range TCLKOUT Rate (MHz) (MHz) (Gbps) SER8_10 FRSYN1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 FRSYN0 125-156.25 62.5-78.125 31.25-39.0625 155.5-175 77.75-87.5 38.875-43.75 250-312.5 250-312.5 250-312.5 311-350 311-350 311-350 2.5-3.125 2.5-3.125 2.5-3.125 2.488-2.8 2.488-2.8 2.488-2.8 CYP32G0401DX forms Ethernet PCS functions using the IEEE802.3z ordered set state machine, Section 36.2.5.2.1 and Figures 36-5 and 36-6. 8B/10B Encoder The CYP32G0401DX contains an 8B/10B encoder to translate the 8-bit input byte to a 10-bit symbol. This function can be bypassed by setting ENCODE LOW. To facilitate alignment of the 10-bit word by the Receive FRAMER, a COMMA character may be generated. This is automatic when in MODE 1, or under the control of TXER (TXK) in MODE 3. The 8B/10B encoder is standards compliant with ANSI/NCITS ASC X3.230-1994 (Fibre Channel), IEEE 802.3z (Gigabit Ethernet), the IBM(R) ESCON(R) and FICONTM channels, and ATM Forum standards for data transport. Notation Conventions The 8B/10B transmission code uses letter notation for describing the bits of an unencoded information octet and a single control variable. Each bit of the unencoded information octet contains either a binary zero or a binary one. A control variable, Z, has either the value D or the value K. When the control variable associated with an unencoded information octet contains the value D, the associated encoded code-group is referred to as a data code-group. When the control variable associated with an unencoded information octet contains the value K, the associated encoded code-group is referred to as a special code-group. The bit notation of A,B,C,D,E,F,G,H for an unencoded information octet is used in the description of the 8B/10B transmission code. The bits A,B,C,D,E,F,G,H are translated to bits a,b,c,d,e,i,f,g,h,j of 10-bit transmission codegroups. See Table 11 at the end of this document for the 8B/10B code-group bit assignments, or refer to Table 36-1 of IEEE802.3. Each valid code-group has been given a name using the following convention: /Dx.y/ for the 256 valid data code-groups, and /Kx.y/ for special control code-groups, where x is the decimal value of bits EDCBA, and y is the decimal value of bits HGF. Valid special code-groups See Table 12 at the end of this document for the valid special code-groups, or refer to Table 36-2 of IEEE802.3. Loop back When loop back is enabled (LBEN = 1) both the high-speed line side data and the byte input data are looped back as follows: * The parallel input data (TXD[7:0], TXEN, TXER) is looped back to the receive side parallel data (RXD[7:0], RXDV, RXER) * The line-received data (RXP and RXN) is looped back and sent to the line driver (TXP and TXN). * In MODE 1 the transmit driver (TXP, TXN) is disabled, as required in IEEE802.3 Section 22.2.4.1.2. Note: LBEN is logically ORed with bit 0.14 of the control register. Line Driver The line driver operates at CML levels, with the output pins TXP and TXN. Electrically, the TXP and TXN look like a differential amplifier with each of its output drains connected to VDD through a 50 resistor. test mode--do not use test mode--do not use The Frequency Synthesizer output is divided to produce a word clock signal that clocks data out of the Transmit Phase Align FIFO. This word clock is available at the TCLKOUT pin. The Frequency Synthesizer output also clocks data out of the parallel-to-serial converter. Transmit Phase Align FIFO The input data TXD[7:0], TXEN, and TXER are clocked into the Phase Align FIFO on the rising edge of the GTXCLK signal. The data is read out of the FIFO with TCLKOUT. The phase of GTXCLK can differ from that of TCLKOUT with any difference and relative jitter absorbed by the FIFO. This is a 10-bit wide by 64-word deep FIFO. Note: To minimize latency through the FIFO, only two data words need be input before data output from the FIFO begins. Parallel-to-Serial Converter The parallel-to-serial converter operates in two modes, eightbit and ten-bit, under the control of the SER8_10 pin, as shown in Table 3. Table 3. Serial Conversion Modes SER8_10 Signal Serializer Function Logic 1 Logic 0 8 to 1 10 to 1 Note: The serializer always outputs data LSB first (Ethernet convention). However in MODE 4 the convention is to transmit MSB first. In order to conform to the desired standard, when the pin SER8_10 is active HIGH, data is presented to the serializer in reverse bit order; i.e., a data word presented at the TXD pins as {D7, D6, D5, D4, D3, D2, D1, D0} is presented to the serializer as {D0, D1, D2, D3, D4, D5, D6, D7}. Ethernet PCS Functions The Ethernet PCS functions are enabled (FRAME = 1) whenever the CYP32G0401DX is operated in MODE 1. This per- Document #: 38-02019 Rev. *C Page 18 of 34 PRELIMINARY Line Receiver A differential signal input on the input pins (RXP, RXN) will be recovered and converted into a binary stream by the receiver. The line receiver is internally biased, and should be capacitively coupled to the driving stage. The RXP and RXN pins are inputs to a differential amplifier with each of the pins connected to VDD/2 through a 150 resistor. Loss of Signal The signal input on the LOS pin may come from a fiber module and indicates if there is a Loss of Signal (LOS) condition. If a LOS condition occurs, the data input is squelched and no data is sent to the data recovery block. When no data edges are present at the inputs to the clock recovery Digital PhaseLocked Loop (DPLL), its output frequency will be locked to the frequency of the transmit Frequency Synthesizer. The polarity of the LOS signal is controlled by the POL pin as shown in Table 4. Table 4. LOS Signal Polarity Control POL LOS RX Data Path 0 0 1 1 0 1 0 1 Enabled Disabled Disabled Enabled CYP32G0401DX A1=0xF6 (8'b11110110), A2=0x28 (8'b00101000), where 0x indicates hexadecimal, and 8'b indicates 8-bit binary. COMMA Framer In MODE 1 and MODE 3 the framing of the 10-bit symbol at the receive side is achieved by a barrel shifter as follows. Two sequential 10-bit symbols of the data are first loaded into the barrel shifter. When a COMMA character is detected at any alignment, that alignment is used to register the current data. 8B/10B Decoder The CYP32G0401DX contains an 8B/10B decoder to translate the 10-bit symbol to the 8-bit byte originally input to the encoder at the other end. The data arrives at the decoder with the 10-bit symbol having already been framed by the COMMA Framer as described above. The 8B/10B decode function can be bypassed by setting ENCODE LOW. Ethernet PCS Functions The Ethernet PCS functions are enabled (FRAME = 1) whenever the CYP32G0401DX is operated in MODE 1. This performs Ethernet PCS functions using the IEEE802.3z receive and synchronization state machines, Section 36.2.5.2.2 and Figures 36-7a, 36-7b, 36-8, and 36-9. Serial-to-Parallel Converter The serial-to-parallel converter operates in two modes, eightbit and ten-bit, under the control of the SER8_10 pin, as shown inTable 3. Receive Elasticity FIFO This is a 12-bit wide by 64-word deep FIFO used to absorb line input jitter and allow phase alignment to the selected output clock. The input data word comprises 10-bit data plus CRS and COL. RXCLK Output The RXCLK pin outputs either a buffered RCLKIN, or the recovered clock. This is determined by the status of LBEN on the rising edge of RESETN as follows: LBEN=0 selects the buffered RCLKIN; LBEN=1 selects the recovered clock. Reset An internal "Power On Reset" function (POR) ensures that following the application of power at all supply pins of the CYP32G0401DX, all circuitry on the device is properly initialized and no external action is required for the device to commence operation. An external RESETN pin reflects the operation of the POR circuit thus: * When POR is active RESETN is driven LOW. * When POR is inactive RESETN is three-stated and an internal pull up resistor (approximately 50 k) establishes the inactive (HIGH) state. The RESETN pin may also be driven from an external device in order to re-initialize the chip regardless of the internal operating state and regardless of the state of POR. In this case RESETN must be driven low for a minimum of two cycles of the reference clock (REFP, REFN), though no other timing relationship between RESETN and the reference clock need exist. Clock and Data Recovery The input data is sent to a DPLL circuit, which recovers the clock. The data edges from the receiver are used to select a phase tapped from the transmit side Frequency Synthesizer. Any difference in frequency between the synthesizer and input data is accommodated by continually adjusting the phase that is tapped. This clock is used to determine the input signal to the deserializer. Deserializer The recovered data is converted into an 8-bit or 10-bit parallel word, with arbitrary alignment. The first bit received is assigned to the least significant bit of that parallel word. Data Framer Note: The data input to this block from the deserializer is in an "LSB first" format (Ethernet style data). When in MODE 4 (indicated by SER8_10=1) the data alignment block reformats the incoming data word to follow the desired convention of "MSB first" i.e., a data word presented by the deserializer as {0, 0, D7, D6, D5, D4, D3, D2, D1, D0} is reformatted to become {0, 0, D0, D1, D2, D3, D4, D5, D6, D7}. A1/A2 Framer In MODE 4 when OOF is active (HIGH), framing is achieved as follows: The alignment state machine will search for the A1/A2 framing sequence and when it is found, will pulse FRP for one cycle. The FRP output will appear on the CRS pin (MODE 4 only). Also, the correctly realigned 8-bit word will be output. If OOF is inactive (low), the previous alignment will be used for the 8-bit word. The framing sequence will consist of 3 A1s followed by 3 A2s. The A1 and A2 characters used for framing are as follows: Document #: 38-02019 Rev. *C Page 19 of 34 PRELIMINARY Built-In-Self-Test Mode (BIST) When operating in MODE 1 and with register 30.8 set, Built-InSelf-Test (BIST) mode is selected. In this mode a pseudo-random data sequence is continuously transmitted instead of the IDLE sequence (or any input data packet). The first character of this sequence is always the Start-of-packet, /S/ character (K27.7) which ensures that a receiver will recognize the data stream as a packet. The pseudo-random sequence is generated by a 16-bit polynomial represented by Xn = Xn+15 EXOR Xn+14. A self-synchronizing comparator function incorporated within the FRAMER checks the incoming data stream against the expected polynomial sequence and generates an error flag when a mismatch occurs. The error flag is logically ORed into the RXER output. The recovered pseudo-random sequence is also decoded and echoed on the RXD bus. Management Interface A management interface on the chip provides serial I/O capabilities as specified in IEEE802.3 Chapter 22. External access to the interface is made through two pins: the management data input/output pin, MDIO, and the management data clock input pin, MDC. Control and status information is serially transferred to and from the CYP32G0401DX on MDIO, with reference timing for the transfer supplied externally on MDC. Control information must be input on MDIO synchronously relative to MDC, allowing the CYP32G0401DX to sample it synchronously. In turn, status information from the CYP32G0401DX CYP32G0401DX is output on MDIO synchronously relative to MDC, and must be synchronously sampled externally. MDC is an aperiodic signal with minimum HIGH and LOW times of 160 ns, and a minimum period of 400 ns. There are no maximum HIGH or LOW times for MDC. Table 5 identifies the available management interface registers, and Table 6 provides the management frame format. The order of transmission is from left to right. Referring to Table 6: PRE = Preamble (32 contiguous logic one bits) ST = Start of frame (01) OP = Operation code (Read = 10, Write = 01) PHYAD = PHY Address (Represented below as "vwxyz") The PHYSICAL MDIO ADDRESS for the CYP32G0401DX is set at the end of reset. When RESETN goes HIGH the three signals ENCODE, FRAME and SER8_10 are locked in as the first three bits (vwx) of PHYAD (See Table 7). The last two bits (yz) identify the channel (See Table 8). For example, PHYAD = 11010 is the address for channel c for the case in which ENCODE = 1, FRAME = 1, and SER8_10 = 0 at the end of reset. REGAD = Register Address TA = Turnaround (delay for turn on/off of bus drivers) DATA = Data (16 bits, bit 15 transmitted first) IDLE = High impedance state on MDIO . Table 5. Management Interface Registers Register Description Register 0 Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 15 Register 30 Register 31 PHY control register (c.f. IEEE802.3 Table 22.7) PHY status register (c.f. IEEE802.3 Table 22.8) PHY identifier register upper bits (c.f. IEEE802.3 Figure 22.12) PHY identifier register lower bits (c.f. IEEE802.3 Figure 22.12) Autonegotiation advertisement register (c.f. IEEE802.3 Table 37.5) Autonegotiation partner ability register (c.f. IEEE802.3 Table 37.6) Autonegotiation expansion (c.f. IEEE802.3 Table 37.7) Extended status register (c.f. IEEE802.3 Table 22.9) Set BIT 8 = 1 for BIST (MODE 1 only). All other bits reserved. (RESERVED) Default 0x3140 0x0109 0x000a 0x3011 0x0060 0x0000 0x0000 0x0000 0x0000 0x0000 Table 6. Management Frame Format[5] PRE READ WRITE 1...1 1...1 ST 01 01 OP 10 01 PHYAD AAAAA AAAAA REGAD RRRRR RRRRR TA Z0 10 DATA DDDDDDDDDDDDDDDD DDDDDDDDDDDDDDDD IDLE Z Z Note: 5. Z = high impedance on PHY's MDIO. It also occurs during READ TA as well as IDLE. Document #: 38-02019 Rev. *C Page 20 of 34 PRELIMINARY Table 7. Chip Portion of PHYAD ENCODE FRAME SER8_10 On Rising Edge of RESETN: 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CYP32G0401DX First 3 Bits (vwx) Chip PHYAD 000 001 010 011 100 101 110 111 VIH(min) VIL(max) MDIO STA sourced VIH(min) 10 ns min. 10 ns min. Table 8. Channel Portion of PHYAD Last 2 Bits (yz) Channel ID Channel PHYAD 00 01 10 11 MDIO/MDC Timing Relationship MDIO (Management Data Input/Output) is a bidirectional signal that can be sourced by the Station Management Entity (STA) or the CYP32G0401DX. When the STA sources the MDIO signal, the STA shall provide a minimum of 10 ns of setup time and a minimum of 10 ns of hold time referenced to the rising edge of MDC. When the MDIO signal is sourced by the CYP32G0401DX, it is sampled by the STA synchronously with respect to the rising edge of MDC. The clock to output delay from the CYP32G0401DX shall be a minimum of 0 ns and a maximum of 300ns. See Figure 5. SSTL_2 Outputs The SSTL_2 outputs meet the requirements of Section 3 of EIA/JESD8-9 for Class II outputs. Line Receiver Requirements The line receiver is compatible with the line driver when capacitively coupled and connected through a backplane of up to 19 inches of properly terminated microstrip or stripline transmission line on FR4. As shown in Figure 6, the RXP and RXN look like a differential amplifier with each of the input pins connected to VDD/2 through a 150 resistor. When inputs are differentially terminated with a 150 resistor, the line termination is nominally 100. Similarly the reference clock inputs, REFP and REFN, look like a differential amplifier with each of the input pins connected to 0.75xVDD through a 150 resistor. This is shown in Figure 7. a b c d MDC VIH(min) MDIO VIL(max) VIL(max) PHY sourced 0 ns min., 300 ns max. Figure 5. MDIO/MDC Timing Relationship External RXP Internal 0.5xVDD 150 INPUT 150 150 RXN Figure 6. Receiver Input Termination External REFP Internal 0.75xVDD 150 INPUT 150 150 REFN Figure 7. Reference Clock Termination Document #: 38-02019 Rev. *C Page 21 of 34 PRELIMINARY Line Driver Requirements The line driver has CML outputs which may be coupled to any fiber module. The TXP and TXN look like a differential amplifier CYP32G0401DX with each of the output drains connected to VDD through a 50 resistor. CYP32G0401DX Operating Conditions Parameter VDD TOP PDISS VDDRIPPLE Description DC Supply Voltage Operating Ambient Temperature Range Power Dissipation Ripple Min. 2.375 -40 --Typ. 2.5 -2.5 -Max. 2.625 85 -50 Unit V C W mV peak-to-peak CYP32G0401DX SSTL_2 Inputs[6] Parameter VREF[7] VIH VIL IIH IIL CI Description Logic Reference Voltage High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Pin Capacitance to ground Min. 0.5xVDD - 5% 1.56 -0.3 --600 -Max. 0.5xVDD + 5% VDD + 0.3 0.94 40 -4 Unit V V V A A pF CYP32G0401DX SSTL_2 Outputs[8] Parameter VREF VOH VOL IOH IOL CO [7] Description Logic reference voltage High Level Output Voltage Low Level Output Voltage High level Output Current Low Level Output Current Pin Capacitance to ground Min. 0.5xVDD - 5% 0.75 x VDD 0 -7.6 --- Max. 0.5xVDD + 5% VDD 0.25 x VDD -7.6 4 Unit V V V mA mA pF CYP32G0401DX Single Ended LVPECL Inputs Parameter VIL VIH Description Low Level Input Voltage High Level Input Voltage Min. VDD - 2.0 VDD - 1.18 Max. VDD - 1.47 VDD - 0.80 Unit V V CYP32G0401DX Differential Reference Clock Inputs (REFP, REFN) - Differential CML Parameter VCM VIDIF[9] |IIH| |IIL| Duty Cycle Description Common Mode Input Voltage Differential Input Voltage Input High Current Input Low Current Percent Duty Cycle Condition --VIDIF = 0.5V VIDIF = 0.5V -Min. 0.65 x VDD 175 1.0 1.0 40 Max. 0.85 x VDD 2000 2.0 2.0 60 Unit V mV peak-to-peak mA mA % Notes: 6. The inputs meet the requirements of Section 2.2 of EIA/JESD8-9. 7. VREF is generated internally to the chip. 8. The outputs meet the requirements of Section 3 of EIA/JESD8-9 for Class I outputs. 9. AC coupled, with each input internally biased to 0.75xVDD through a 150 resistor, as shown in Figure 7. Document #: 38-02019 Rev. *C Page 22 of 34 PRELIMINARY CYP32G0401DX CYP32G0401DX Transmit Data Input Timing Parameter tTXDS tTXDH tGTXCLKH tGTXCLKL tGTXCLK Description Set-up time to GTXCLK rising TXD[7:0]x, TXENx, TXERx Hold time from GTXCLK rising TXD[7:0]x, TXENx, TXERx GTXCLKx high GTXCLKx low GTXCLKx period Min. 700 200 1.42 1.42 2.84 Max. -----Unit ps ps ns ns ns CYP32G0401DX Receive Data Output Timing Parameter tRXDH tRCLKINH tRCLKINL tRCLKIN Description Hold time with respect to RXCLKx rising RXD[7:0]X, RXERx, RXDVx, CRSx, COLx RCLKINx high RCLKINx low RCLKINx period Min. 250 1.42 1.42 2.84 Max. ----Unit ps ns ns ns CYP32G0401DX RXPx-RXNx Line Receiver Inputs - Differential CML Parameter VCM VIDIF |IIH| |IIL| LOSSIR Description Common Mode Input Voltage Differential Input Voltage Input High Current Input Low Current Input Return Loss[10] Condition --VIDIF = 0.5V VIDIF = 0.5V -Min. 0.4 x VDD 175 1.0 1.0 10 Max. 0.6 x VDD 2000 2.0 2.0 -Unit V mV peak-to-peak mA mA dB CYP32G0401DX TXPx-TXNx Line Driver Outputs - Differential CML PARAMETER VoSE VoDIFF tRISE tFALL DESCRIPTION Single Ended Output Voltage[11] Differential Output Voltage[11] Rise Time (10% to 90%) Fall Time (10% to 90%) MIN 400 800 110 110 MAX 950 1900 200 200 UNITS mV peak-to-peak mV peak-to-peak ps ps Notes: 10. Using receiver input termination shown in Figure 6. 11. Voltage swings measured with 100 load AC coupled line to line. Document #: 38-02019 Rev. *C Page 23 of 34 PRELIMINARY Switching Waveforms for the CYP32G0401DX Transmitter Transmit Interface Write Timing[12] CYP32G0401DX tGTXCLK GTXCLKx TXD[7:0]x TXENx TXERx tTXDH TCLKOUT Timing[13] tGTXCLKH tGTXCLKL tTXDS FRSYN0 = 0 FRSYN1 = 0 tREFCLK tREFCLKH tTCLKOUT tREFCLKL REFLCK TCLKOUT FRSYN0 = 1 FRSYN1 = 0 tREFCLK REFLCK tTCLKOUT TCLKOUT tREFCLKH tREFCLKL FRSYN0 = 0 FRSYN1 = 1 tREFCLK REFLCK tTCLKOUT TCLKOUT tREFCLKH tREFCLKL Notes: 12. Lowercase suffix `x' is used to denote channels a, b, c, and d. 13. TCLKOUT is phase locked to REFCLK and is a multiple (2x, 4x, or 8x) of the REFCLK frequency. See Table 2 for further details. Document #: 38-02019 Rev. *C Page 24 of 34 PRELIMINARY CYP32G0401DX Switching Waveforms for the CYP32G0401DX Receiver Receive Interface Read Timing[14] tRCLKIN tRCLKINH RCLKINx RXD[7:0]x RXERx RXDVx CRSx COLx RXCLKx [14 tRCLKINL tRXDH Note: 14. RXCLKx is delayed in phase from RCLKINx. Document #: 38-02019 Rev. *C Page 25 of 34 PRELIMINARY ANSI X3.230 (FC-PH) Codes and Notation Information to be transmitted over a serial link is encoded 8 bits at a time into a 10-bit Transmission Character and then sent serially, bit by bit. Information received over a serial link is collected ten bits at a time, and those Transmission Characters that are used for data (Data Characters) are decoded into the correct eight-bit codes. The 10-bit Transmission Code supports all 256 8-bit combinations. Some of the remaining Transmission Characters (Special Characters) are used for functions other than data transmission. The primary rationale for use of a Transmission Code is to improve the transmission characteristics of a serial link. The encoding defined by the Transmission Code ensures that sufficient transitions are present in the serial bit stream to make clock recovery possible at the Receiver. Such encoding also greatly increases the likelihood of detecting any single or multiple bit errors that may occur during transmission and reception of information. In addition, some Special Characters of the Transmission Code selected by Fibre Channel Standard consist of a distinct and easily recognizable bit pattern (the Special Character COMMA) that assists a Receiver in achieving word alignment on the incoming bit stream. Notation Conventions The documentation for the 8B/10B Transmission Code uses letter notation for the bits in an 8-bit byte. Fibre Channel Standard notation uses a bit notation of A, B, C, D, E, F, G, H for the 8-bit byte for the raw 8-bit data, and the letters a, b, c, d, e, i, f, g, h, j for encoded 10-bit data. There is a correspondence between bit A and bit a, B and b, C and c, D and d, E and e, F and f, G and g, and H and h. Bits i and j are derived, respectively, from (A,B,C,D,E) and (F,G,H). The bit labeled A in the description of the 8B/10B Transmission Code corresponds to bit 0 in the numbering scheme of the FC2 specification, B corresponds to bit 1, as shown below. FC-2 bit designation-- 76543210 HOTLink D/Q designation-- 7 6 5 4 3 2 1 0 8B/10B bit designation-- HGFEDCBA To clarify this correspondence, the following example shows the conversion from an FC-2 Valid Data Byte to a Transmission Character (using 8B/10B Transmission Code notation) FC-2 45 Bits: 7654 3210 0100 0101 Converted to 8B/10B notation (note carefully that the order of bits is reversed): Data Byte Name D5.2 Bits:ABCDEFGH 10100 010 CYP32G0401DX order, and the y is the decimal value of the binary number composed of the bits H, G, and F in that order. When c is set to K, xx and y are derived by comparing the encoded bit patterns of the Special Character to those patterns derived from encoded Valid Data bytes and selecting the names of the patterns most similar to the encoded bit patterns of the Special Character. Under the above conventions, the Transmission Character used for the examples above, is referred to by the name D5.2. The Special Character K29.7 is so named because the first six bits (abcdei) of this character make up a bit pattern similar to that resulting from the encoding of the unencoded 11101 pattern (29), and because the second four bits (fghj) make up a bit pattern similar to that resulting from the encoding of the unencoded 111 pattern (7). Note: This definition of the 10-bit Transmission Code is based on (and is in basic agreement with) the following references, which describe the same 10-bit transmission code. A.X. Widmer and P.A. Franaszek. "A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code" IBM Journal of Research and Development, 27, No. 5: 440-451 (September, 1983). U.S. Patent 4,486,739. Peter A. Franaszek and Albert X. Widmer. "Byte-Oriented DC Balanced (0.4) 8B/10B Partitioned Block Transmission Code" (December 4, 1984). Fibre Channel Physical and Signaling Interface (ANS X3.230- 1994 ANSI FC-PH Standard). IBM Enterprise Systems Architecture/390 ESCON I/O Interface (document number SA22-7202). 8B/10B Transmission Code The following information describes how the tables are used for both generating valid Transmission Characters (encoding) and checking the validity of received Transmission Characters (decoding). It also specifies the ordering rules to be followed when transmitting the bits within a character and the characters within the higher-level constructs specified by the standard. Transmission Order Within the definition of the 8B/10B Transmission Code, the bit positions of the Transmission Characters are labeled a, b, c, d, e, i, f, g, h, j. Bit "a" is transmitted first followed by bits b, c, d, e, i, f, g, h, and j in that order. (Note that bit i is transmitted between bit e and bit f, rather than in alphabetical order.) Valid and Invalid Transmission Characters The following tables define the valid Data Characters and valid Special Characters (K characters), respectively. The tables are used for both generating valid Transmission Characters (encoding) and checking the validity of received Transmission Characters (decoding). In the tables, each Valid-Data-byte or Special-Character-code entry has two columns that represent two (not necessarily different) Transmission Characters. The two columns correspond to the current value of the running disparity ("Current RD-" or "Current RD+"). Running disparity is a binary parameter with either the value negative (-) or the value positive (+). After powering on, the Transmitter will assume a negative value for its initial running disparity. Upon transmission of any Transmission Character, the transmitter selects the proper version of the Transmission Character based on the current running disparity value, and the Transmitter calculates a new Page 26 of 34 Translated to a transmission Character in the 8B/10B Transmission Code: Bits: abcdeifghj 1010010101 Each valid Transmission Character of the 8B/10B Transmission Code has been given a name using the following convention: cxx.y, where c is used to show whether the Transmission Character is a Data Character (c is set to D) or a Special Character (c is set to K). When c is set to D, xx is the decimal value of the binary number composed of the bits E, D, C, B, and A in that Document #: 38-02019 Rev. *C PRELIMINARY value for its running disparity based on the contents of the transmitted character. After powering on, the Receiver may assume either a positive or negative value for its initial running disparity. Upon reception of any Transmission Character, the Receiver decides whether the Transmission Character is valid or invalid according to the following rules and tables and calculates a new value for its Running Disparity based on the contents of the received character. The following rules for running disparity are used to calculate the new running-disparity value for Transmission Characters that have been transmitted (Transmitter's running disparity) and that have been received (Receiver's running disparity). Running disparity for a Transmission Character shall be calculated from sub-blocks, where the first six bits (abcdei) form one sub-block and the second four bits (fghj) form the other subblock. Running disparity at the beginning of the 6-bit sub-block is the running disparity at the end of the previous Transmission Character. Running disparity at the beginning of the 4-bit subblock is the running disparity at the end of the 6-bit sub-block. Running disparity at the end of the Transmission Character is the running disparity at the end of the 4-bit sub-block. Running disparity for the sub-blocks are calculated as follows: 1. Running disparity at the end of any sub-block is positive if the sub-block contains more ones than zeros. It is also positive at the end of the 6-bit sub-block if the 6-bit sub-block is 000111, and it is positive at the end of the 4-bit sub-block if the 4-bit sub-block is 0011. 2. Running disparity at the end of any sub-block is negative if the sub-block contains more zeros than ones. It is also negative at the end of the 6-bit sub-block if the 6-bit sub-block is 111000, and it is negative at the end of the 4-bit sub-block if the 4-bit sub-block is 1100. 3. Otherwise, running disparity at the end of the sub-block is the same as at the beginning of the sub-block. Use of the Tables for Generating Transmission Characters The appropriate entry in the table are found for the Valid Data byte or the Special Character byte for which a Transmission Character is to be generated (encoded). The current value of the Transmitter's running disparity shall be used to select the Transmission Character from its corresponding column. For each Transmission Character transmitted, a new value of the running disparity shall be calculated. This new value shall be used as the Transmitter's current running disparity for the next Valid Data byte or Special Character byte to be encoded and CYP32G0401DX transmitted. Table 9 shows naming notations and examples of valid transmission characters. Use of the Tables for Checking the Validity of Received Transmission Characters The column corresponding to the current value of the Receiver's running disparity is searched for the received Transmission Character. If the received Transmission Character is found in the proper column, then the Transmission Character is valid and the associated Data byte or Special Character code is determined (decoded). If the received Transmission Character is not found in that column, then the Transmission Character is invalid. This is called a code violation. Independent of the Transmission Character's validity, the received Transmission Character is used to calculate a new value of running disparity. The new value is used as the Receiver's current running disparity for the next received Transmission Character. Table 9. Valid Transmission Characters Data DIN or QOUT Byte Name D0.0 D1.0 D2.0 . . D5.2 . . D30.7 D31.7 765 000 000 000 . . 010 . . 111 111 43210 00000 00001 00010 . . 00010 1 . . 11110 11111 Hex Value 00 01 02 . . 45 . . FE FF Detection of a code violation does not necessarily show that the Transmission Character in which the code violation was detected is in error. Code violations may result from a prior error that altered the running disparity of the bit stream which did not result in a detectable error at the Transmission Character in which the error occurred. Table 10 shows an example of this behavior. Table 10. Code Violations Resulting from Prior Errors RD Transmitted data character Transmitted bit stream Bit stream after error Decoded data character - - - - Character D21.1 101010 1001 101010 1011 D21.0 RD - - + + Character D10.2 010101 0101 010101 0101 D10.2 RD - - + + Character D23.5 111010 1010 111010 1010 Code Violation RD + + + + Document #: 38-02019 Rev. *C Page 27 of 34 PRELIMINARY Table 11. Valid Data Characters (MODE 1 and MODE 3) Data Byte Name D0.0 D1.0 D2.0 D3.0 D4.0 D5.0 D6.0 D7.0 D8.0 D9.0 D10.0 D11.0 D12.0 D13.0 D14.0 D15.0 D16.0 D17.0 D18.0 D19.0 D20.0 D21.0 D22.0 D23.0 D24.0 D25.0 D26.0 D27.0 D28.0 D29.0 D30.0 D31.0 Bits HGF EDCBA 000 00000 000 00001 000 00010 000 00011 000 00100 000 00101 000 00110 000 00111 000 01000 000 01001 000 01010 000 01011 000 01100 000 01101 000 01110 000 01111 000 10000 000 10001 000 10010 000 10011 000 10100 000 10101 000 10110 000 10111 000 11000 000 11001 000 11010 000 11011 000 11100 000 11101 000 11110 000 11111 Current RD- abcdei fghj 100111 0100 011101 0100 101101 0100 110001 1011 110101 0100 101001 1011 011001 1011 111000 1011 111001 0100 100101 1011 010101 1011 110100 1011 001101 1011 101100 1011 011100 1011 010111 0100 011011 0100 100011 1011 010011 1011 110010 1011 001011 1011 101010 1011 011010 1011 111010 0100 110011 0100 100110 1011 010110 1011 110110 0100 001110 1011 101110 0100 011110 0100 101011 0100 Current RD+ abcdei fghj 011000 1011 100010 1011 010010 1011 110001 0100 001010 1011 101001 0100 011001 0100 000111 0100 000110 1011 100101 0100 010101 0100 110100 0100 001101 0100 101100 0100 011100 0100 101000 1011 100100 1011 100011 0100 010011 0100 110010 0100 001011 0100 101010 0100 011010 0100 000101 1011 001100 1011 100110 0100 010110 0100 001001 1011 001110 0100 010001 1011 100001 1011 010100 1011 Data Byte Name D0.1 D1.1 D2.1 D3.1 D4.1 D5.1 D6.1 D7.1 D8.1 D9.1 D10.1 D11.1 D12.1 D13.1 D14.1 D15.1 D16.1 D17.1 D18.1 D19.1 D20.1 D21.1 D22.1 D23.1 D24.1 D25.1 D26.1 D27.1 D28.1 D29.1 D30.1 D31.1 Bits HGF EDCBA 001 00000 001 00001 001 00010 001 00011 001 00100 001 00101 001 00110 001 00111 001 01000 001 01001 001 01010 001 01011 001 01100 001 01101 001 01110 001 01111 001 10000 001 10001 001 10010 001 10011 001 10100 001 10101 001 10110 001 10111 001 11000 001 11001 001 11010 001 11011 001 11100 001 11101 001 11110 001 11111 CYP32G0401DX Current RD- abcdei fghj 100111 1001 011101 1001 101101 1001 110001 1001 110101 1001 101001 1001 011001 1001 111000 1001 111001 1001 100101 1001 010101 1001 110100 1001 001101 1001 101100 1001 011100 1001 010111 1001 011011 1001 100011 1001 010011 1001 110010 1001 001011 1001 101010 1001 011010 1001 111010 1001 110011 1001 100110 1001 010110 1001 110110 1001 001110 1001 101110 1001 011110 1001 101011 1001 Current RD+ abcdei fghj 011000 1001 100010 1001 010010 1001 110001 1001 001010 1001 101001 1001 011001 1001 000111 1001 000110 1001 100101 1001 010101 1001 110100 1001 001101 1001 101100 1001 011100 1001 101000 1001 100100 1001 100011 1001 010011 1001 110010 1001 001011 1001 101010 1001 011010 1001 000101 1001 001100 1001 100110 1001 010110 1001 001001 1001 001110 1001 010001 1001 100001 1001 010100 1001 Document #: 38-02019 Rev. *C Page 28 of 34 PRELIMINARY Table 11. Valid Data Characters (MODE 1 and MODE 3) (continued) Data Byte Name D0.2 D1.2 D2.2 D3.2 D4.2 D5.2 D6.2 D7.2 D8.2 D9.2 D10.2 D11.2 D12.2 D13.2 D14.2 D15.2 D16.2 D17.2 D18.2 D19.2 D20.2 D21.2 D22.2 D23.2 D24.2 D25.2 D26.2 D27.2 D28.2 D29.2 D30.2 D31.2 Bits HGF EDCBA 010 00000 010 00001 010 00010 010 00011 010 00100 010 00101 010 00110 010 00111 010 01000 010 01001 010 01010 010 01011 010 01100 010 01101 010 01110 010 01111 010 10000 010 10001 010 10010 010 10011 010 10100 010 10101 010 10110 010 10111 010 11000 010 11001 010 11010 010 11011 010 11100 010 11101 010 11110 010 11111 Current RD- abcdei fghj 100111 0101 011101 0101 101101 0101 110001 0101 110101 0101 101001 0101 011001 0101 111000 0101 111001 0101 100101 0101 010101 0101 110100 0101 001101 0101 101100 0101 011100 0101 010111 0101 011011 0101 100011 0101 010011 0101 110010 0101 001011 0101 101010 0101 011010 0101 111010 0101 110011 0101 100110 0101 010110 0101 110110 0101 001110 0101 101110 0101 011110 0101 101011 0101 Current RD+ abcdei fghj 011000 0101 100010 0101 010010 0101 110001 0101 001010 0101 101001 0101 011001 0101 000111 0101 000110 0101 100101 0101 010101 0101 110100 0101 001101 0101 101100 0101 011100 0101 101000 0101 100100 0101 100011 0101 010011 0101 110010 0101 001011 0101 101010 0101 011010 0101 000101 0101 001100 0101 100110 0101 010110 0101 001001 0101 001110 0101 010001 0101 100001 0101 010100 0101 Data Byte Name D0.3 D1.3 D2.3 D3.3 D4.3 D5.3 D6.3 D7.3 D8.3 D9.3 D10.3 D11.3 D12.3 D13.3 D14.3 D15.3 D16.3 D17.3 D18.3 D19.3 D20.3 D21.3 D22.3 D23.3 D24.3 D25.3 D26.3 D27.3 D28.3 D29.3 D30.3 D31.3 Bits HGF EDCBA 011 00000 011 00001 011 00010 011 00011 011 00100 011 00101 011 00110 011 00111 011 01000 011 01001 011 01010 011 01011 011 01100 011 01101 011 01110 011 01111 011 10000 011 10001 011 10010 011 10011 011 10100 011 10101 011 10110 011 10111 011 11000 011 11001 011 11010 011 11011 011 11100 011 11101 011 11110 011 11111 CYP32G0401DX Current RD- abcdei fghj 100111 0011 011101 0011 101101 0011 110001 1100 110101 0011 101001 1100 011001 1100 111000 1100 111001 0011 100101 1100 010101 1100 110100 1100 001101 1100 101100 1100 011100 1100 010111 0011 011011 0011 100011 1100 010011 1100 110010 1100 001011 1100 101010 1100 011010 1100 111010 0011 110011 0011 100110 1100 010110 1100 110110 0011 001110 1100 101110 0011 011110 0011 101011 0011 Current RD+ abcdei fghj 011000 1100 100010 1100 010010 1100 110001 0011 001010 1100 101001 0011 011001 0011 000111 0011 000110 1100 100101 0011 010101 0011 110100 0011 001101 0011 101100 0011 011100 0011 101000 1100 100100 1100 100011 0011 010011 0011 110010 0011 001011 0011 101010 0011 011010 0011 000101 1100 001100 1100 100110 0011 010110 0011 001001 1100 001110 0011 010001 1100 100001 1100 010100 1100 Document #: 38-02019 Rev. *C Page 29 of 34 PRELIMINARY Table 11. Valid Data Characters (MODE 1 and MODE 3) (continued) Data Byte Name D0.4 D1.4 D2.4 D3.4 D4.4 D5.4 D6.4 D7.4 D8.4 D9.4 D10.4 D11.4 D12.4 D13.4 D14.4 D15.4 D16.4 D17.4 D18.4 D19.4 D20.4 D21.4 D22.4 D23.4 D24.4 D25.4 D26.4 D27.4 D28.4 D29.4 D30.4 D31.4 Bits HGF EDCBA 100 00000 100 00001 100 00010 100 00011 100 00100 100 00101 100 00110 100 00111 100 01000 100 01001 100 01010 100 01011 100 01100 100 01101 100 01110 100 01111 100 10000 100 10001 100 10010 100 10011 100 10100 100 10101 100 10110 100 10111 100 11000 100 11001 100 11010 100 11011 100 11100 100 11101 100 11110 100 11111 Current RD- abcdei fghj 100111 0010 011101 0010 101101 0010 110001 1101 110101 0010 101001 1101 011001 1101 111000 1101 111001 0010 100101 1101 010101 1101 110100 1101 001101 1101 101100 1101 011100 1101 010111 0010 011011 0010 100011 1101 010011 1101 110010 1101 001011 1101 101010 1101 011010 1101 111010 0010 110011 0010 100110 1101 010110 1101 110110 0010 001110 1101 101110 0010 011110 0010 101011 0010 Current RD+ abcdei fghj 011000 1101 100010 1101 010010 1101 110001 0010 001010 1101 101001 0010 011001 0010 000111 0010 000110 1101 100101 0010 010101 0010 110100 0010 001101 0010 101100 0010 011100 0010 101000 1101 100100 1101 100011 0010 010011 0010 110010 0010 001011 0010 101010 0010 011010 0010 000101 1101 001100 1101 100110 0010 010110 0010 001001 1101 001110 0010 010001 1101 100001 1101 010100 1101 Data Byte Name D0.5 D1.5 D2.5 D3.5 D4.5 D5.5 D6.5 D7.5 D8.5 D9.5 D10.5 D11.5 D12.5 D13.5 D14.5 D15.5 D16.5 D17.5 D18.5 D19.5 D20.5 D21.5 D22.5 D23.5 D24.5 D25.5 D26.5 D27.5 D28.5 D29.5 D30.5 D31.5 Bits HGF EDCBA 101 00000 101 00001 101 00010 101 00011 101 00100 101 00101 101 00110 101 00111 101 01000 101 01001 101 01010 101 01011 101 01100 101 01101 101 01110 101 01111 101 10000 101 10001 101 10010 101 10011 101 10100 101 10101 101 10110 101 10111 101 11000 101 11001 101 11010 101 11011 101 11100 101 11101 101 11110 101 11111 CYP32G0401DX Current RD- abcdei fghj 100111 1010 011101 1010 101101 1010 110001 1010 110101 1010 101001 1010 011001 1010 111000 1010 111001 1010 100101 1010 010101 1010 110100 1010 001101 1010 101100 1010 011100 1010 010111 1010 011011 1010 100011 1010 010011 1010 110010 1010 001011 1010 101010 1010 011010 1010 111010 1010 110011 1010 100110 1010 010110 1010 110110 1010 001110 1010 101110 1010 011110 1010 101011 1010 Current RD+ abcdei fghj 011000 1010 100010 1010 010010 1010 110001 1010 001010 1010 101001 1010 011001 1010 000111 1010 000110 1010 100101 1010 010101 1010 110100 1010 001101 1010 101100 1010 011100 1010 101000 1010 100100 1010 100011 1010 010011 1010 110010 1010 001011 1010 101010 1010 011010 1010 000101 1010 001100 1010 100110 1010 010110 1010 001001 1010 001110 1010 010001 1010 100001 1010 010100 1010 Document #: 38-02019 Rev. *C Page 30 of 34 PRELIMINARY Table 11. Valid Data Characters (MODE 1 and MODE 3) (continued) Data Byte Name D0.6 D1.6 D2.6 D3.6 D4.6 D5.6 D6.6 D7.6 D8.6 D9.6 D10.6 D11.6 D12.6 D13.6 D14.6 D15.6 D16.6 D17.6 D18.6 D19.6 D20.6 D21.6 D22.6 D23.6 D24.6 D25.6 D26.6 D27.6 D28.6 D29.6 D30.6 D31.6 Bits HGF EDCBA 110 00000 110 00001 110 00010 110 00011 110 00100 110 00101 110 00110 110 00111 110 01000 110 01001 110 01010 110 01011 110 01100 110 01101 110 01110 110 01111 110 10000 110 10001 110 10010 110 10011 110 10100 110 10101 110 10110 110 10111 110 11000 110 11001 110 11010 110 11011 110 11100 110 11101 110 11110 110 11111 Current RD- abcdei fghj 100111 0110 011101 0110 101101 0110 110001 0110 110101 0110 101001 0110 011001 0110 111000 0110 111001 0110 100101 0110 010101 0110 110100 0110 001101 0110 101100 0110 011100 0110 010111 0110 011011 0110 100011 0110 010011 0110 110010 0110 001011 0110 101010 0110 011010 0110 111010 0110 110011 0110 100110 0110 010110 0110 110110 0110 001110 0110 101110 0110 011110 0110 101011 0110 Current RD+ abcdei fghj 011000 0110 100010 0110 010010 0110 110001 0110 001010 0110 101001 0110 011001 0110 000111 0110 000110 0110 100101 0110 010101 0110 110100 0110 001101 0110 101100 0110 011100 0110 101000 0110 100100 0110 100011 0110 010011 0110 110010 0110 001011 0110 101010 0110 011010 0110 000101 0110 001100 0110 100110 0110 010110 0110 001001 0110 001110 0110 010001 0110 100001 0110 010100 0110 Data Byte Name D0.7 D1.7 D2.7 D3.7 D4.7 D5.7 D6.7 D7.7 D8.7 D9.7 D10.7 D11.7 D12.7 D13.7 D14.7 D15.7 D16.7 D17.7 D18.7 D19.7 D20.7 D21.7 D22.7 D23.7 D24.7 D25.7 D26.7 D27.7 D28.7 D29.7 D30.7 D31.7 Bits HGF EDCBA 111 00000 111 00001 111 00010 111 00011 111 00100 111 00101 111 00110 111 00111 111 01000 111 01001 111 01010 111 01011 111 01100 111 01101 111 01110 111 01111 111 10000 111 10001 111 10010 111 10011 111 10100 111 10101 111 10110 111 10111 111 11000 111 11001 111 11010 111 11011 111 11100 111 11101 111 11110 111 11111 CYP32G0401DX Current RD- abcdei fghj 100111 0001 011101 0001 101101 0001 110001 1110 110101 0001 101001 1110 011001 1110 111000 1110 111001 0001 100101 1110 010101 1110 110100 1110 001101 1110 101100 1110 011100 1110 010111 0001 011011 0001 100011 0111 010011 0111 110010 1110 001011 0111 101010 1110 011010 1110 111010 0001 110011 0001 100110 1110 010110 1110 110110 0001 001110 1110 101110 0001 011110 0001 101011 0001 Current RD+ abcdei fghj 011000 1110 100010 1110 010010 1110 110001 0001 001010 1110 101001 0001 011001 0001 000111 0001 000110 1110 100101 0001 010101 0001 110100 1000 001101 0001 101100 1000 011100 1000 101000 1110 100100 1110 100011 0001 010011 0001 110010 0001 001011 0001 101010 0001 011010 0001 000101 1110 001100 1110 100110 0001 010110 0001 001001 1110 001110 0001 010001 1110 100001 1110 010100 1110 Document #: 38-02019 Rev. *C Page 31 of 34 PRELIMINARY CYP32G0401DX Table 12. Valid Special Code-Groups (MODE 1 and MODE 3) Code Group Name K28.0 K28.1 K28.2 K28.3 K28.4 K28.5 K28.6 K28.7 K23.7 K27.7 K29.7 K30.7 Notes: 15. Reserved. 16. Contains a COMMA. Octet Value 1C 3C 5C 7C 9C BC DC FC F7 FB FD FE Octet Bits HGF EDCBA 000 11100 001 11100 010 11100 011 11100 100 11100 101 11100 110 11100 111 11100 111 10111 111 11011 111 11101 111 11110 Current RD abcdei fghj 001111 0100 001111 1001 001111 0101 001111 0011 001111 0010 001111 1010 001111 0110 001111 1000 111010 1000 110110 1000 101110 1000 011110 1000 Current RD + abcdei fghj 110000 1011 110000 0110 110000 1010 110000 1100 110000 1101 110000 0101 110000 1001 110000 0111 000101 0111 001001 0111 010001 0111 100001 0111 Notes 15 15, 16 15 15 15 16 15 15, 16 Document #: 38-02019 Rev. *C Page 32 of 34 PRELIMINARY Ordering Information Speed Standard Standard Ordering Code CYP32G0401DX-BGC CYP32G0401DX-BGI Package Name 256 L2BGA 256 L2BGA Package Type CYP32G0401DX Operating Range Commercial Industrial 256-Ball Thermally Enhanced Ball Grid Array 256-Ball Thermally Enhanced Ball Grid Array HOTLink is a registered trademark and HOTLink-III is a trademark of Cypress Semiconductor Corporation. InfiniBand is a trademark of the InfiniBand Trade Association. IBM and ESCON are registered trademarks and FICON is a trademark of International Business Machines. Package Diagram 256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256 51-85123-*C Document #: 38-02019 Rev. *C Page 33 of 34 (c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CYP32G0401DX Document Title: CYP32G0401DX Multi-Gigabit Multi-Mode Quad HOTLink-III (TM) Transceiver (Preliminary) Document Number: 38-02019 REV. ** *A *B ECN NO. 107382 108153 110119 Issue Date 06/19/01 07/17/01 09/26/01 Orig. of Change KBN KBN GHW New Data Sheet Changed 256 BGA package diagram to 256 L2BGA (#51-85123) Minor rewording of Features section Added Functional Description, Block Level Diagram, Pin Descriptions, Electrical Parameters, Waveforms, 8B/10B Codes, Switching Parameters Advance to Preliminary Reduced Static Discharge Voltage maximum rating to 500V Description of Change *C 111408 11/09/01 EK Document #: 38-02019 Rev. *C Page 34 of 34 |
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